1. Field of the Invention
The present invention relates to a semiconductor device designing method and apparatus as well as a memory media that is stored with macro information, which is used to design a semiconductor device. In particular, it relates to techniques for designing differing sizes of semiconductor devices by combining macros.
2. Description of the Related Arts
Japanese Patent Laid-open No. Hei 10-261718 describes an ASIC (application specific integrated circuit), which is a type of semiconductor device. More specifically it describes a technique of designing an ASIC by laying out macro cells of varying types of circuits, such as a CPU core, a RAM, and a ROM, on a semiconductor chip, and then interconnecting them.
FIG. 1 is a flowchart that shows a general design procedure of a macro-based semiconductor device. As shown in this Figure, in step S1 the specifications of functions and characteristics of a to-be-developed semiconductor device are planned. Afterwards, small-scale circuit blocks necessary for satisfying these specifications are planned, and then registered as macros in a library. In step S2 some of these small-scale macros are combined so as to design a larger-scale functional block and then register it in the said library. Next in step S3, these small-scale and larger-scale macros along with circuit elements, input/output terminals, etc. are then arranged in predetermined areas, respectively, thus determining their rough layout on the semiconductor chip.
There exists a hard macro and a soft macro. In each hard macro, the layout of the circuit elements and interconnects, which make up each macro and which connect them as necessary, are fixed on the semiconductor chip. Conversely, the soft macro does not fix the layout of its circuit elements like the hard macro does, but fixes the relatively connective relationship among circuit elements, which is represented by a netlist, etc. or a functional level description. In the conventional semiconductor device plan, each circuit is formed into either a hard macro or a soft macro, and as a result the semiconductor devices are designed in a hierarchic fashion such that small-scale macros are combined to form large-scale macros and the floor plan is determined based upon these types of macros.
Next, the chip size of the semiconductor device made necessary by this floor plan is determined in step S4. The package that can accommodate the semiconductor chip with this chip size is determined in step S5. Then in step S6 the intervals between respective adjacent pads that will be placed on the semiconductor chip are determined based upon this chip size and package. Next, once the intervals between the respective pads are determined in this fashion, the layout of the circuit elements on the semiconductor chip is fixed based upon the above macro in step S7. With this layout design, not only is the arrangement of each macro on the semiconductor chip determined, but also the interconnect placement between each macro, between each macro and circuit element, and between these and the input/output terminals are all determined.
For example, the A/D converter is well known as one of the elements that form circuits in semiconductor devices. This A/D converter is comprised of a main body that converts an analog signal into a digital signal, a reference voltage generator that supplies the main body with a reference voltage, and single or multi-channel input circuits that supply an analog signal to the main body. For designing the layout of an A/D converter of this kind, the A/D converter is changed into macro form in a manner such that the main body, the reference voltage generator, and the input/output circuit are placed adjacent to each other and also close to the pads corresponding to this A/D converter. Interconnects among them are then automatically formed.
Afterwards, the connection of this macro to macros related to other circuits forming the semiconductor device performs the arrangement of interconnects throughout the entire semiconductor device and completes the layout design. By completing the layout design in this fashion, the interconnect length and interconnect width are determined, the parasitic resistance and parasitic capacitance to the interconnects are calculated and the performance of the semiconductor device is tested by a simulation device in step S8. Then if there are deficiencies in performance, each of the above design processes are reexamined and design modifications are implemented.
In this type of conventional design of semiconductor device, if deficiencies in the performance of the semiconductor device are found in the results of the performance testing, it is necessary to go back to the process causing the deficiency and reexamine each of the above design processes. If in order to fulfill the delay specifications, the layout related to the other circuits needs to be changed and the layout of the main body of the A/D converter circuit is accordingly changed, then the voltage output from the reference voltage generator changes. Because of this, the size of each resistance inside the reference voltage generator needs to be changed in accordance with the interconnect length in the updated layout. Moreover, the reference voltage generator must be accordingly subjected to a re-layout. Also when the A/D converter is embedded in another product or a semiconductor device, the functional differences among each semiconductor device require differing chip sizes and packages. This results in the output of each design process always including a new design operation for each semiconductor device.
Therefore, in the conventional design of a semiconductor device, the design efficiency is extremely poor. Especially remarkable in recent years is the tendency towards micro-production of various models of semiconductor devices, and in order to meet the demand of a shortened delivery time, it is necessary for the semiconductor design efficiency to be drastically improved. Improving the design efficiency of semiconductor devises is a technical issue that must be solved immediately.
Furthermore, in single-chip microcomputers, etc., an A/D converter is used to take in analog signals, whereas a D/A converter is used to output an analog signal. This type of A/D converter and D/A converter convert analog signals to digital and digital signals to analog, respectively, and are comprised of the reference voltage generator, which assists them in performing signal conversion.
FIG. 2 is a circuit diagram of an example of this kind of reference voltage generator. As shown in this Figure, the reference voltage generator is formed in a manner such that: reference voltage Pavref is received from the outside; the resistance ladder comprised of resistance R1, R, . . . R2 is used to divide the voltage between the Pavref and Pagnd; and any one of the partial voltages obtained though this structure (which represent reference voltages for comparison) is supplied to the comparison/conversion circuit through one of the switches. Each reference voltage used for comparison is compared to an analog input signal by the comparison/conversion circuit, thus quantizing the analog input signal.
When a semiconductor device has this type of reference voltage generator, there is a problem with the conventional semiconductor device designing method where the performance of the reference voltage generator differs in each semiconductor device. Namely, because the intervals between adjacent pads on the semiconductor chip are determined by the chip size in the above manner, the placement of the reference voltage generator relative to each pad changes according to chip size. Furthermore, because the region at which the reference voltage generator is arranged upon the semiconductor chip is determined based on the arrangement of other circuits, the distance between the reference voltage generator and the pads differs with each product or each semiconductor device.
This causes the interconnect length between the pad for the reference voltage Pavref and the reference voltage generator and also between the pad for the Pagnd (analog ground) and the reference voltage generator to differ. Accordingly, the parasitic resistances r1 and r2 differ as shown in FIG. 2 so that the performance of the reference voltage generator corresponds to chip size, or in other words, the said performance differs in each semiconductor device. Therefore, even if the circuit formation and layout of each reference voltage generator are completely identical, each reference voltage for comparison will be different because the above parasitic resistances r1 and r2 are different due to the different chip sizes. Conventionally, this problem with the changes in the parasitic resistances r1 and r2 is solved by adjusting the resistance R1 and/or the resistance R2. So far, the problematic points have been described using the example of an A/D converter, however even in the D/A converters, the phase comparators in PLL circuits, the constant current generating circuits and the like, the same problems develop with layout changes.
For example in the field of mobile communication devices, package (i.e., chip) downsizing and energy efficiency are demanded of core semiconductor devises such as single-chip microcomputers. In order to respond to these demands, there is a countermeasure to further increase the degree of integration in semiconductor chips and to lower the operating voltage. However, when semiconductor chips become highly integrated, noise can easily enter analog circuits from digital circuits, thus the quality of the analog signal deteriorates.
Taking the above problems into account the present invention has the following objectives:
1. To improve the design efficiency for a semiconductor device.
2. To design a downsized semiconductor device.
3. To design a semiconductor device with high-level integration.
4. To hold down the performance deterioration of analog signals caused by noise from digital circuits.
5. To prevent the reference voltage circuit performance from differing in each semiconductor device made into new products.
6. To prevent the performance of A/D converters and D/A converters from differing in each product or each semiconductor device.
According to an aspect of the present invention, a method of designing a semiconductor device is provided and is comprised of the step of assigning pads (a2 to a4) with their intervals being fixed on a semiconductor chip for a hard macro (A); and laying out the said hard macro (A) on the said semiconductor chip, in conformity with the location of the said pads (a2 to a4); wherein the said hard macro (A) includes layout/interconnect data of a layout-sensitive part (A) of a circuit (A, B) with its corresponding pads (a2 to a4) with their intervals being fixed. An example of this method is illustrated in FIGS. 4, 6, 7, 8 and 10.
According to an aspect of the present invention, a semiconductor device designing apparatus is provided and is comprised of a macro storage unit (2 to 6), which is stored with a hard macro that includes layout/interconnect data of a layout-sensitive part (A) in a circuit (A, B) and corresponding pads (a2 to a4) with their intervals being fixed; and a layout design unit (7, 1000), which lays out the said hard macro, stored in the said macro storage unit, on a semiconductor chip in the manner such that given interval fixed pads on the said semiconductor chip can correspond to the said pads (a2 to a4) in the said hard macro. An example of this apparatus is illustrated in FIGS. 3 and 10.
According to an aspect of the present invention, a memory medium for storing data for access by an application program being executed on a data processing system is provided and is comprised of hard macro data which is stored in the said memory medium and which includes layout/interconnect data of a layout-sensitive part of a circuit with its corresponding pads; wherein the intervals between the said pads are fixed.